This invention generally relates to microprocessors, and more specifically to improvements in access and data transfer to cache storage resources, systems, and methods of making.
Microprocessors are general-purpose processors that provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever-increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general-purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general-purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
A shared cache can also be associated with the shared memory to improve storage access time for each of the processors. Various caches handle write transactions in different manners. A first embodiment of a cache performs write through, in which data is written directly to backing memory. If the address was also present in the cache, a hit, the cache is updated. A second embodiment of a cache performs write allocation. In this case, if a write address misses in the cache, then a cache line is allocated to receive the data being written. A third embodiment of a cache performs copy-back. In this case, data is not immediately written directly to backing memory, but is first written only to the cache using write allocation. A dirty bit is set to indicate incoherent cache data. When the line is evicted, then the dirty data is written to backing memory.
Modular programming builds a computer program by combining independently executable units of computer code (known as modules), and by tying modules together with additional computer code. Features and functionality that may not be provided by a single module may be added to a computer program by using additional modules.
The design of a computer program unit known as a task (or function) is often accomplished through modular programming, where a specific task is comprised of one module and the additional computer code needed to complete the task (if any additional code is needed). However, a task may be defined as broadly as a grouping of modules and additional computer codes, or, as narrowly as a single assembly-type stepwise command. A computer program may be processed (also called xe2x80x9crunxe2x80x9d or xe2x80x9cexecutedxe2x80x9d) in a variety of manners. In task processing, a computer may process computer code one task at a time, or may process multiple tasks simultaneously, for example.
Various tasks may operate on a set of data stored in memory. The various tasks may be executed on various processors that have shared access to the memory and cache. Accordingly, there is needed a system and method for managing a shared cache taking into account resource capabilities and capacity, and other task processing needs.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. In accordance with a first embodiment of the invention, a method is provided for operating a digital system that has a shared cache memory and an associated back-up memory. During operation of the system, a write allocation policy is established, software programs are executed and memory transactions are performed. According to an aspect of the present invention, a write transaction request is initiated to an address in the back-up memory and an attribute signal is provided with the write transaction request. Write allocation in the cache memory is performed in a selective manner in response to the attribute signal in accordance with the write allocation policy.
In another embodiment, write allocation in the cache is responsive to the write allocate policy such that write allocation is performed in a selective manner in accordance to the attribute signal for a first write policy state and write allocation is always performed in accordance to the attribute signal for a second write policy state.
In another embodiment, write allocation in the cache is defined on a page basis. A set of address regions (pages) is defined within an address space of the back-up memory. A write allocation attribute bit value is assigned to each of at least a portion of the set of address ranges. In this manner, the attribute signal is responsive to the value of the write allocation attribute bit assigned to an address region that includes the address of the write transaction request.
Advantageously, the usage of a shared cache in a multiprocessor system can be optimized by controlling write allocation on a page by page basis and refined in accordance with a write allocation policy in order to improve performance of tasks operating on the various processors of the system and to also reduce power consumption. Advantageously, the write attribute policy can be changed over time based on a currently executing task or on other factors known to the OS, for example.